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5 4 3 2 1 VCC SWITCH L50II0 Schematics Rev:C PAGE CONTENT 1. Cover Page 2. System Block Diagram 3. POWER BLOCK DIAGRAM L50II0 REV:A P/N LIST D 4. YONAH CPU HOST & CPU Thermal Sensor 6. CPU_POWER 7. CLK GEN ICS9LPR310-CLK 8. NB(1)_Host 9. NB(2)_DMI/Configuation/PM 10. NB(3)_VGA_TV_LVDS_PCIEx16* I/F 11. NB(4)_DDR2 I/F 12. C PCB ASSY P/N GPIO & POWER CONSU 5. D PCB P/N NB(5)_POWER 13. NB(6)_POWER 14. DDR2 _SO-DIMM 15. SB(1)_CPU/SATA/IDE/RTC/LPC/AZALIA 16. SB(2)_PCI/GPIO/SMBUS/PM/DMI/USB/PCIEx1 17. SB(3)_Power 18. IEEE1394A & CARD READER 19. LAN 10/100 20. HDD/ODD/FAN/SMART PWR 21. EC IT8510E 22. C LCD PWR / INVERT CONN / LVDS CONN/ROM 23. MINI CARD & NEW CARD & 3G & BT 24. Daughter BD CONN 25. CRT CONN WITH PR8800 B B 26. +5V&+3V(MAX8734A) 27. +CPU CORE(MAX8771) 28. +1.5V&+1.8V(OZ813) & +2.5V(RT9173B) 29. +1.05V(OZ818) & +1.2V(RT9173B) & +0.9V(RT9173B) 30. +1.0V_VGA & +1.8V_VGA(OZ813) 31. POWER ON SWITCH FUNC. 32. A Charger func.(TL594) & DC IN CON & BATTERY CONN 33 Every Ver. Histor 37GL50200-C0 PCB MAIN BD FOR L50II0 REV:C 82GL50200-C0 M/B ASSY FOR L50II0 hexainf@hotmail.com GRATIS - FOR FREE A Name of Part Project Cover Page L50II0 Rev C Sheet Date: Tuesday, April 25, 2006 ISSUED BY DC2 5 4 3 2 3255 1 / 33 UNIWILL COMPUTER CORP. 1 5 4 3 2 1 CLK GEN ICS 925083 INTEL CPU Yonah/Merom Dual/Singal D D CRT FSB533/667 TV S-OUT North Bridge DDR2 Channel A DDR2 SO-DIMM1/533/667 DDR2 Channel B DDR2 SO-DIMM2/533/667 INTEL 945GM 14"~15" LCD 14.318 MHz DMI BUS PATA I/F INTEL ICH7M AZALIA MODEM AUDIO CODEC EAR/SPDIF SATA HDD South Bridge AZALIA I/F MIC ODD MASTER SATA I/F C ALC880 PATA HDD PCI I/F AMP TPA6011A LAN RTL8100CL C IEEE 1394/CardReader OZ128T PCI I/F 1XPCI-EXPRESS B B MINI CARD NEW CARD SPK-L Wireless LAN SPK-R USB USB PR8800 USB NEW-Card USB BlueTooth LPC BUS EC ITE 8510 SMART PWR VGA SENSOR CPU SENSOR ADM1032 ADM1032 Touch PAD CHARGER SYS Temp Thermistor DDR Temp Thermistor BATTERY SWITCH LCD CTRL USB 3G-WCDMA Debug PORT BIOS FAN_CPU K/B LED PWR ON CTRL A A Name of Part Project BLOCK_DIAGRAM L50II0 Rev C Sheet Date: Tuesday, April 25, 2006 3255 5 4 3 2 2 / 33 UNIWILL COMPUTER CORP. 1 5 4 3 POWER BLOCK DIAGRAM 2 VIN 1 +1.8VS ISL6224 D VID0 VID1 VID2 VID3 VID4 VID5 +0.9VS RT9173B RSS090N03 VIN SC451 D RSS090N03 SI4362 CPU_CORE +1.8V AO4422 +5VA VIN RSS090N03 AO4422 POWER Sequence +5VS +5V SI4835 +3VA,+5VA,+12VA C SC1404 C PWRSW +12VA . +3.3VS_ON SI2301 +5VS,+12VS +12VS +3.3VS . +1.5VS_ON VIN +1.5VS +3.3VA +3.3VS +2.5VS AO4422 RSS090N03 1ms . +1.05VS_ON . +1.8V_DDR_ON RT9173B +1.8VS +1.05VS +3.3V/ ＞0.9A SI4835 1ms 1ms . RSMRST# . PWRBTN# . +5V_ON B 50ms 10ms 1s B 5.8ms +5V VIN +1.5VS/4.5A +1.5V 40ms +3.3V +2.5V ISL6225 RSS090N03 . +1.8V_ON AO4422 +1.8V +1.05V +1.5V VIN . Vcore_ON +1.05VS/4.5A 7ms Vcore RSS090N03 AO4422 . PWROK/VR_PWRGD +1.05V/1.8A 110ms H_PWRGD PCIRST#/PLTRST# A hexainf@hotmail.com GRATIS - FOR FREE A CPURST# Name of Part POWER DIAGRAM & SEQUENCE . EC Control Pin Project L50II0 Rev C Sheet Date: Tuesday, April 25, 2006 3255 5 4 3 2 3 / 33 UNIWILL COMPUTER CORP. 1 5 ICH6-M GPIO D GPI0 GP7 GP8 GPI11 GPI12 GPI13 GPO18 GPO19 GPO20 GPO21 GPO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 BM_BUSY# EC_EXTSMI# SMB_ALERT# PM_STPPCI_ICH# PM_STPCPU_ICH# TPM_EN SATA0_GP PNLSW1 PNLSW2 PNLSW0 PM_CLKRUN# C B 4 3 ITE8510E ITE8510E GPIO GPCF0 GPCF1 GPCF2 GPCF3 GPCF4 GPCF5 GPCF6 GPCF7 GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 GPI6 GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 GPH6 GPH7 GPG4 GPG5 GPG6 GPG7 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 CPU 2

L19IA0L50II0X72IA6